SignalTap II是很實用的FPGA debug tool，一個QuartusII所提供的系統級除錯工具，透過JTAG connector即時擷取與顯示FPGA內部訊號狀態，並且可以設定多種觸發條件，就如同使用真的邏輯分析儀一樣。

How does it work?

藉由引入Megafunction的ELA (Embedded Logic Analyzer)以擷取internal signal data，資料存放在FPGA內部的memory (RAM)，再透過JTAG傳遞到QuartusII分析

耗用FPGA資源：

• Using LEs\ALMs resource for ELA (Embedded Logic Analyzer) megafunction implement, and using Memory for sample storage.

• LE count is a function of the number of channels & trigger levels

• Memory block count is a function of number of channels & sample depth

Waveform Export：

• Comma Separated Values File (.csv)

• Table File (.tbl)

• Value Change Dump File (.vcd)

• Vector Waveform File (.vwf)

• Joint Photographic Experts Group File (.jpeg)

• Bitmap File (.bmp)

SignalTap II supports up to 1,024 channels and 128K samples on a single device.

1. Create a new SignalTap II File (.stp file)

2. Add instances and add nodes to each instance

3. Assign a clock to each instance

4. Set sample depth and trigger conditions

5. Compile the design

6. Program the device.

7. Acquire and analyze signal data.

1. Create a new SignalTap II File. (.stp file) 

   

Tool \ SignalTap II Logic Analyzer

  or

File \ New \ Verification/Debugging Files \ SignalTap II Logic Analyzer File

一開始的預設檔名是stp1.stp，可以Save as成其他檔名

• Instance Manager： set  and run instance
  To create, delete, rename, and set logic analyzer instances in the SignalTap II File. It displays all instances in the current SignalTap II File, and helps you to check the amount of resource usage that each logic analyzer requires on the device. You can start multiple logic analyzers at the same time by selecting them and clicking Run Analysis on the Processing menu.

• JTAG Chain configuration：

• Node List and Trigger condition Columns： select signals to monitor  and set trigger conditions
  You can specify advanced triggers by selecting Advanced in the Trigger Conditions column in the Setup tab of the SignalTap II Logic Analyzer window. 

• Signal configuration \ Trigger： manage data capture and signal configuration
  A trigger is a pattern of logic events defined by logic levels, clock edges, and logical expressions. It supports multilevel triggering, multiple trigger positions, multiple segments, and external trigger events. 

Advanced triggers provide the ability to build flexible, user-defined logic expressions and conditions based on the data values of internal buses or nodes. On the Advanced Trigger tab, you can drag and drop symbols from the Node List and the Object Library to create a logical expression composed of logical, comparison, bitwise, reduction, shift operators, and event counters.

2. Add instances and add nodes to each instance. 

   

預設有一個SignalTap Instance "auto_signaltap_0"，可以按滑鼠右鍵"Create Instance"新增其他Instance

選定要設定哪一個Instance定時，下方的Node List and Trigger Condition window會相映顯示。此時在empty list雙擊滑鼠左鍵出現Node Finder，可以選擇" pre-synthesis"、" post-fitting" Filter以指定node。

Pre-synthesis：Nodes available after analysis & elaboration, but before synthesis
      Post-fitting：Nodes available after Fitter optimizations and place-and-route

Disable "Data Enable" will reduce the SignalTap resource (memory)
      Disable "Trigger Enable" will reduce the SignalTap resource (logic cell count)

3. Assign a clock to each instance. 

   

Use global, fastest clock available for best results, and the clock signal cannot be monitored as data.

Data written to memory on every sample clock rising edge.

External clock pin created automatically if clock unassigned.

4. Set sample depth and trigger conditions  

   

• Sample Depth：-Set number of samples stored for each data signal (0~128K)

• RAM Type：-Set RAM type of the device selected. 選擇不同的FPGA device，可以使用的RAM type也不同，下圖左是Cyclone device、圖右是StratixII

  

• Buffer Type：Default buffer type is "circular", and "Segmented" turn off。After trigger event occurs, post-trigger data is collected until buffer fills up

• Trigger Position：Three default positions，Pre (12% before trigger, 88% after)、Center (50% before, 50% after)、Post (88% before, 12% after)

• Trigger Conditions：最多可以指定10級的rigger conditions，當這裡指定時，左邊的node list會出現對應數目的Trigger condition columns

• Trigger signal
  -- Trigger in：可以指定以某一個訊號作為trigger，預設名稱auto_stp_trigger_out_n，可以在Pin Planner內指定pin assignment
  -- Trigger out：當trigger event發生，輸出一個indicated signal ，預設名稱auto_stp_trigger_out_n，可以在Pin Planner內指定pin assignment

5. Compile the design. 

   

使用SignalTap II可能會影響原本的performance(因為P&R會被改變)，所以使用SignalTap II要用Incremental Compilation，視SignalTap II為一個design partition。

先關閉SignalTap做一次full compilation

把原design的Netlist Type設成"Post-Fit"

打開SignalTap，再做一次start compilation

6. Program the device. 

   

Setup JTAG

7. Acquire and analyze signal data