本公众号【读芯树:duxinshu_PD】主要介绍数字集成电路物理设计相关知识,才疏学浅,如有错误,欢迎指正交流学习。
这是集成电路物理设计的第五个系列【signoff】的第十六篇文章,本篇文章主要介绍grid check Analysis相关内容:
01
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Grid Check Analysis
电源网络的连接不充分极易造成大的IR Drop问题。
在APR的早期,如完成placement和CTS之后可以进行gridcheck检查电源网络的连接是否充分。
gridcheck甚至不需要STA timing文件和SPEF文件。
perform gridcheck: 估算所有instance的电阻极大值进行估算。
perform res_calc: 计算指定instance的有效电阻值。
如果instance有较差的power/ground连接,则该instance在gridcheck的report中会有较大的电阻值。
02
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Redhawk cmd
bsub -n 8 -Is readhawk -f gridcheck.tcl -P topname
##################gridcheck.tcl##################
import gsr gridcheck.gsr
setup design
setup analysis_mode static
perform extraction -power -ground -
perform gridcheck -limit 10000000 -o grid_check.rpt
explore design
export db ir_gridcheck
exit
03
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Global System Requirement
APACHE_FILES clean
CACHE_DIR ./tmp
MULTI_THREADS 8
TEMPERATURE 85
TECHNOLOGY 12
ENABLE_ATE 0
USE_DEF_VIARULE 1
USE_LIB_MAX_CAP 1
REXTRACTION_DETAIL_LEVEL 1
EXTRACT_INTERNAL_NET 1
SPLIT_VIA_ARRAY VIA1 0.01
MERGE_VIA_METAL 1
VIA_BASED_PIN_CURRENT_DIST 1
LOWEST_METAL M1
ITERATIVE_SOLVER 0
IGNORE_LEF_DEF_MISMATCH 1
IGNORE_LIB_CHECK 1
IGNORE_DEF_ERROR 1
IGNORE_PGARC_ERROR 1
IGNORE_GDSMEM_ERROR 0
PUSH_PININST 1
PUSG_PG_PININST 1
ADD_LEF_CELL_FOR_POWER 0
DEF_TRUE_PATH_EXTENSION 1
TOP_CELL design_name
FREQ 500e6
TOGGLE_RATE 0.3 2.0
INPUT_TRANSITION 0.1ns
VDD_NETS {VDD 0.8}
GND_NETS {VSS 0}
TEMPERATURE_EM 110
EM_LENGTH_USE_MAX_LENGTH 1
USE_DRAWN_WIDTH_FOR_EM 1
USE_DRAWN_WIDTH_FOR_EM_LOOKUP 1
TECH_FILE {apache_design.tech}
LEF_FILES {tech.lef cell.lef}
LIB_FILES {cell1.lib cell2.lib}
DEF_FILES {block.def block design.def top}
BLOCK_STA_FILES {FREQ_OF_MISSING_INSTANCE 500e6 design_name design.timing}
CELL_RC_FILE {cell_name cell.spef design_name design.spef}
NET_LOAD_FILE {net_load.list}
VCD_FILE {design_name design.vcd
FILE_TYPE VCD
FRONT_PATH '/test/'
SUBSTITUTE_PATH ''
SELECT_RANGE -1 -1
TRUE_TIME 1
}
PAD_FILES {./design.ploc}
GDS_FILES {}
GSC_FILES {}
APL_FILES {}
DECAP_CELLS_FILES {dcap_cell.list}
IGNORE_CELLS_FILES {fill_cell.list}
IGNORE_LEF_CELL_PIN_FILE {ignore_pin.list}
DYNAMIC_SIMULATIN_TIME 10e9
DYNAMIC_TIME_STEP 10e12
DYNAMIC_PRESIM_TIME -1
VCD_X_LOGIC_STATE 3
VCD_TIME_ALIGNMENT 1
POWER_VCD_COVERED_THRESHOLD 0.001
04
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参考文献
RedHawk User Guide
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