Understanding PLL jitter from timing perspective to ensure design closure

PLL jitter is one of the unwanted but unavoidable components of PLL. With the latest designs working in Giga Hertz frequencies to boost system throughput, PLL jitter is causing even more problems to designers. Moreover, as we enter into sub-90 nm technologies, new, unheard of factors (or factors that were topics of/for research work only until a few years ago) are denting timing margins while we need better and accurate timing signoffs than ever before. Considering all these factors, PLL jitter occupies an important role in signing off chip-level timing  analysis.

In this article, various aspects of PLL jitter in order to achieve robust timing signoff are discussed.  We will dig into various cases where PLL jitter impacts timing and ways to tackle this in our timing signoff.  We will also discuss solutions at the system architecture level to minimize impact of PLL jitter.

What is Jitter

PLL or Phase Locked Loop is the first choice of designers to supply high frequency clocks with 50% duty cycle to their system. However, due to the noise factor, there is undesired timing variation in edges of output clock from PLL. This deviation of clock edges from its ideal position is termed as jitter.

 

 

 Figure 1

 

This deviation can decrease as well as increase overall clock period and can occur on both leading and trailing clock edges.

This jitter has multiple sources like thermal noise due to crystal vibration, noise inherent in electrical systems, power-supply noise, EMI etc. We will not go into the details of these sources. We will now discuss the different types of jitters.

Type of PLL jitter

1) Cycle to Cycle jitter: Cycle to Cycle jitter is the maximum difference of time period between two consecutive clock cycles. This is the most important parameter for timing analysis.

2) Long term (Accumulated) jitter: Long term jitter is the accumulative maximum difference of clock output transition from its ideal position over a large number of cycles. Once PLL crosses this limit, PLL gets unlocked again.

3) Half Cycle jitter: Half cycle jitter is the maximum difference of clock output transition from its ideal position over a half period of clock.

Duty Cycle

Most of the clock sources do not generate an ideal 50 % duty cycle clock. For designs where both edges of the clock are used for data transfer, duty cycle of  clock becomes very important and  any variation in duty cycle must be considered during timing analysis.  

PLL Jitter and Timing Analysis

As discussed above, due to PLL jitter, clock waveform cannot be assumed to be ideal and this effect should be considered in timing analysis.

Let us discuss the impact of cycle to cycle and half cycle jitter.

Cycle to Cycle Jitter

There are ways to model this pessimism in timing analysis. One of the easiest ways is to apply extra uncertainty in setup timing. This method works fine if there is single clock source going to all registers in design and there are no multi-cycle paths in design. Generally in design, there are many clocks dividers working on main source clock to generate divided clocks to various modules.

The important point to note is that effective time period will reduce in divided clock due to possibility of summation of jitter in same direction in multiple cycles. So if we have 100Mhz(10ns) clock from PLL and source clock has +/-500ps jitter and if we generate divide by 2 (50Mhz clock) and divide by 4 (25Mhz clock) using main 100Mhz source clock, the minimum time period  for different clocks considering jitter will be:

Example 1:

T 100Mhz = 10 -0.5 = 9.5ns
T 50Mhz  = 20- 0.5 *2 = 19ns
T 25 MHz = 40 -0.5*4 = 38ns

The above example shows a flat extra pessimism of 500ps will not be sufficient for 50 MHz and 25 MHz clock.

Even if there is no divided clock but multi-cycle paths exist in our design, again a flat uncertainty will result in inaccurate analysis because multi-cycle paths like divided clocks can have effective jitter more than in single cycle in the worst case.

So the best way to consider this cycle to cycle jitter is to adjust time period with jitter for source clock and hence time period of other divided clocks will be automatically adjusted.  STA tool will interpret the generated clock definition of these divided clocks with main clocks source as master clock. The problem to model jitter in multi-cycle paths will also be solved by using this approach.

A factor that should be considered while applying cycle-2-cycle jitter impact in frequency is long term jitter. Overall impact of jitter on divided clock should not be more than long term jitter, though in most of the cases, either this factor will not come in the picture or timing paths working on this clock will not be setup critical. 

Half Cycle Jitter/Duty cycle variation

As discussed earlier, both leading and trailing edges of clock can be shifted with respect to ideal position due to jitter. Half cycle jitter changes duty cycle of clock. 

Both half cycle jitter and duty cycle variation impact half cycle timing paths (where one register is clocked by leading edge and other register is clocked by trailing edge) in design. These variations are modeled as clock uncertainty in static timing analysis, but these uncertainties are applied between rise edge and fall edge of the clock and vice-versa.

Let us take an example:

 

Half Cycle jitter impact in multiple synchronous clocks

It is often seen that most of the times a STA engineer takes care of above half cycle jitter by applying clock uncertainty but modern designs are way more complex than this simple case. Nowadays, designs have multiple clock sources, clock dividers also. It is very important to make sure while analyzing half cycle jitter impact in these cases that design is not over-constrained or over-relaxed .

We will here consider few cases where thorough analysis is required to check the need of half cycle uncertainty.  Let us take a general case where few flops are working on rising edge of clock CLKIN and few flops are working on fall edge of clock CLKIN. Similarly let us consider a clock dividing/gating circuitry which is generating clock CLKOUT with CLKIN as input clock. Also let us assume there are both type of registers working on either rise edge of CLKOUT or fall edge of CLKOUT.

 

                                                             Figure 2


Now we will consider some cases where this Clock Dividing/Gating Logic is generating CLKOUT having different possible edge relationship with respect to input CLKIN in each case.

Case 1

Complex punch through clock

                                                            Figure 3


Punch through clocks are commonly generated using clock gating logic and are not with 50% duty cycle.

In the above case, duty cycle uncertainty between CLKIN and CLKOUT will be from rise_edge to fall_edge and vice-versa as in the case of CLK in Example 2.

                                                                 Table 1

Case 2

Complex punch through inverted clock

Let us take another case when generated clock is inverted div/2 punch through clock:

                                                         Figure 4


For CLKIN, duty cycle variation happen across the fall edge, while in CLKOUT, this effect is across rise edge of clock waveform. In this case, duty cycle uncertainty will affect the path from rise-edge of CLKIN/CLKOUT to rise-edge of CLKOUT/CLKIN and also from fall-edge to fall-edge.

 

                                                                  Table 2



Case 3:

Generated clock is divide/2 with 50% duty cycle

                                                                    
                                                             Figure 5

Now we will consider some cases where this Clock Dividing/Gating Logic is generating CLKOUT having different possible edge relationship with respect to input CLKIN in each case.

Output clock is derived using rise-edge of input clock. This form of generated clock will not have duty cycle variation of source clock. It will have cycle-to- cycle jitter of source and that is modeled in frequency. If there are valid timing paths between CLKIN and CLKOUT, they will have inter clock uncertainty. This uncertainty will be there only for the paths originating and terminating at the fall-edge of the source clock CLKIN. The table below shows inter clock uncertainty to be applicable in this case.

                                                             Table 3


Architecture Solutions to avoid Jitter

From the above cases, it is very clear that PLL Jitter adds lot of complexity in accurate timing analysis and architecture solutions must be explored to minimize jitter.

The most desirable solution is to go for PLL that has minimum output jitter. Noise due to various reasons – thermal noise, VCO noise, power supply noise- is one of the most primary reasons for jittery PLL output and the PLL designer should fix these issues to generate low jitter clock.

Once you have decided to use particular PLL, solutions at SoC level should be explored to minimize the impact of pll jitter. One of the most common and effective way to eliminate half cycle jitter is to use divide by two clock version of double the input frequency at PLL source.  Output clock will be generated only on either rising edges or falling edges of input clock and half cycle jitter will be eliminated.

                                                           Figure 6


It should also be architecturally explored that whether one can minimize interaction between rise and fall edges by intelligently designing the RTL logic.

Another important guideline, although not related to PLL jitter, is to design clock tree with symmetrical clock tree buffers so that duty cycle variation due to the difference in rise and fall delays of clock tree elements can be minimized. This will help in minimizing further degradation of clock duty cycle and will help in meeting already reduced timing margins caused by inherent half cycle jitter.

Conclusion

As we are working on high frequency designs, PLL is the first choice of designers to provide high frequency clock to design, but PLL comes with inherent limitations of jitter. Due to jitter, output clock is not ideal and can have variations in its clock period and duty cycle. STA engineer should take care of these variations in his timing margins in order to ensure accurate timing analysis. The cycle to cycle jitter only impacts setup timing and the best way to take care of this jitter is to recalculate effective time period based on jitter value. The half cycle jitter is another important issue, although sometimes mistakenly ignored, factored in calculating timing margins. One should carefully analyze edge relationships between multiple synchronous clocks to check whether one needs to apply half cycle jitter uncertainty between these clocks.  

 

About the authors:

 

Ashish Goel is a Principal Design Engineer at Freescale Semiconductor, India. He has 12 years of industry experience in various fields of VLSI, such as Static Timing Analysis, RTL Design, Physical design and Formal technologies. He has been with Freescale since three years. Ashish also holds multiple patents in field of FPGA architecture and can be reached at http://www.techonlineindia.com/techonline/news_and_analysis/169002/[e-mail].

 

Amol Agarwal is working at Freescale as Lead Design Engineer and has experience of more than 6 years.  He is working in the physical design team with STA & Synthesis as area of specialization.  He has been involved in several block-level and chip-level designs in technology ranging from 250-nm to 40-nm. He can be reached at http://www.techonlineindia.com/techonline/news_and_analysis/169002/[e-mail].

 

 

Neha Mathur is a Senior Design Engineer at Freescale,  focusing on static timing analysis and timing closure of complete SoCs. She holds a bachelor's degree in electronics from Shri Ramdeobaba Kamla Nehru Engineering College, Nagpur University (Nagpur, India). She can be reached at http://www.techonlineindia.com/techonline/news_and_analysis/169002/[e-mail].