By default, we expect every timing path to meet setup time in a single clock cycle. However, we can also specify that some data is captured only after a specified number of clock cycles. Till then, the data at the capturing flop will not be used. Of course your circuit should be designed in such a way for this kind of behaviour to be valid. This is usually a large combinational block between two registers. It is important to specify the multicycle paths to synthesis and place&route tools, as the tools will otherwise try to fix these paths.
This timing exception is specified by the SDC command “set_multicycle_path”. This lets you specify the number of clock cycles required for the path.
Let us take the timing path from the previous post Setup & Hold. Let us say the datapath requires 3 clock cycles.
The clock diagram is given below. Assume the launch is at edge 1 of CLK.
We can specify the timing relationship as
set_multicycle_path 3 -setup -from FF1/CP -to FF2/D
Once you have this specification, the STA tool takes the clock edge 4 as the capturing edge for FF2. By default, the hold is always checked one clock edge prior to setup edge. Hence the hold will be checked at edge 3. If you want the hold check to be done at another edge, say the launch edge itself, a set_multicycle_path -hold should also be given along with the setup specification. set_multicycle_path 1 -hold -from FF1/CP -to FF2/D will move the hold edge by one clock cycle from the default hold edge. i.e. to 2. set_multicycle_path 2 -hold will move the hold checking edge 2 cycles from the default hold edge. i.e. to clock edge 1, which is the default hold edge without any set_multicycle_path specified.
