To avoid this, a special kind of clock gating cells are used, that synchronizes the EN with a clock edge. These are call integrated clock gating cells or ICG.
There are two commonly used ICG cell types.
- Using AND gate with high EN
The following design uses a negative edge triggered latch to synchronize the EN signal to the CLK. The GCLK is available only when the latch o/p is high. GCLK is held low when EN is low. - Using OR gate with high EN
The following design uses a positive edge triggered latch. GCLK is held high when EN is low.Note that the latch o/p is inverted at the OR input. Hence, the clock is passed through when this i/p gets a low.