Michael Kelly, vice president of advanced packaging development and integration at Amkor, sat down with Semiconductor Engineering to talk about advanced packaging and the challenges with the technology. What follows are excerpts of that discussion.
Amkor 先进封装开发和集成副总裁 Michael Kelly 与 Semiconductor Engineering 坐下来讨论先进封装以及该技术面临的挑战。以下是该讨论的摘录。
SE: We’re in the midst of a huge semiconductor demand cycle. What’s driving that?
SE：我们正处于巨大的半导体需求周期之中。是什么推动了这一点？
SE: IC packaging isn’t new, but years ago it was largely in the background. A package simply encapsulated and protected a chip. Recently, packaging has become more important. What changed?
SE：IC 封装并不新鲜，但几年前它基本上还处于幕后。封装只是封装和保护芯片。最近，包装变得更加重要。发生了什么变化？
Kelly: Packaging has been around for a long time. It always has been this thing that connects the real world, via a circuit board, to the integrated circuit. You need to get the signals from the silicon out to something that people can use to create products. The package was simply mounted on a circuit board. For a long time, there were more developments in semiconductor processing. You had new transistors and architectures. You had new ways of boosting the performance with the same transistor or better transistors. That has been the story for over 50 years. That’s where the key technology was centered. It was inside the chip. Over time, more electrical functionality was built in and around the central processor. Then, it became very complicated. There were different voltage domains and transistor requirements. And then we hit a new juncture. To keep increasing the performance at a reasonable cost, you can’t just keep putting all of that functionality into what is going to be a relatively big chip in a cutting-edge node. The wafers are going to be expensive. You can increase your performance, but the cost is going to go up in a fashion that doesn’t justify the performance gains. So you need to come up with a better economic model to maintain that performance to cost ratio. One way is to pull the high-speed assets, like your processor cores, into the leading-edge nodes and keep the rest of the chips at other nodes. You can get the same performance by combining dies of mixed nodes in a package at the same or a lower cost. That required flexibility is influenced by the business market you’re talking about. For example, I can use a chiplet that I designed in 10 different products and recombine them in different ways at the package level. Then I won’t need to have a full-custom system-on-a-chip (SoC) design for every one of those products. So the package is the little envelope that’s pulling all the pieces together, making these heterogeneous constructions more powerful. As a result, you have a shorter time-to-market than if you do a custom design every time.
凯利：包装已经存在很长时间了。它始终是通过电路板将现实世界连接到集成电路的东西。您需要将信号从芯片传输到人们可以用来创建产品的东西。该封装被简单地安装在电路板上。长期以来，半导体加工有了更多的发展。你有了新的晶体管和架构。您可以使用相同的晶体管或更好的晶体管来提高性能的新方法。 50多年来，这个故事一直如此。这就是关键技术的集中之处。它在芯片内部。随着时间的推移，中央处理器内部和周围内置了更多的电气功能。然后，事情就变得非常复杂了。存在不同的电压域和晶体管要求。然后我们到达了一个新的关口。为了以合理的成本不断提高性能，您不能只是将所有功能都放入尖端节点中相对较大的芯片中。晶圆将会很昂贵。您可以提高性能，但成本会以一种无法证明性能收益合理的方式上升。因此，您需要提出更好的经济模型来维持性能成本比。一种方法是将高速资产（例如处理器内核）拉入前沿节点，并将其余芯片保留在其他节点。您可以通过以相同或更低的成本将混合节点的芯片组合到一个封装中来获得相同的性能。所需的灵活性受到您所讨论的商业市场的影响。例如，我可以在 10 种不同的产品中使用我设计的小芯片，并在封装级别以不同的方式重新组合它们。 这样我就不需要为每一种产品都进行完全定制的片上系统 (SoC) 设计。所以这个包就像一个小信封，它将所有的部分拉在一起，使这些异构结构变得更加强大。因此，与每次进行定制设计相比，您的上市时间会更短。
SE: What are the other issues?
SE：还有哪些其他问题？
Kelly: Some companies don’t have enough designers to design a custom SoC for all marketplaces. But if I design chiplets, and then mix-and-match them for various market segments, that’s a better use of my design talent. Packaging is in the mix here. So if you disaggregate an SoC, you need to re-aggregate the IP blocks at the package level to have a fully functional product. That’s pushing the package to do more things. You require fine lines to keep things integrated. You need to manage thermal waste heat or power. You need to deliver power to an increasingly power-hungry device. That’s putting extra demands on the package.
Kelly：有些公司没有足够的设计师来为所有市场设计定制 SoC。但如果我设计小芯片，然后针对不同的细分市场将它们混合搭配，那就可以更好地利用我的设计才能。包装在这里是混合在一起的。因此，如果您分解 SoC，则需要在封装级别重新聚合 IP 块才能获得功能齐全的产品。这正在推动该计划做更多的事情。你需要细线来保持事物的整合。您需要管理热废热或电力。您需要为日益耗电的设备供电。这对包装提出了额外的要求。
SE: What are the big concerns here?
SE：这里最令人担忧的是什么？
Kelly: Power dissipation and power usage are big challenges. It’s hitting home in the packaging industry because of the integration at the package level. Unfortunately, silicon generates a lot of wasted heat. It’s not thermally efficient. You need to dump the heat somewhere. We have to participate in the ways that we can, which is between the die and the package edge. We have to make that as thermally efficient as possible for whoever is doing the thermal dissipation in the final product, whether that’s in a phone case or a water cooler in the data center. How much actual electrical current we have to deliver into a high-performance package is also getting interesting. Power is not going down, but voltages are sliding down. To deliver the same total power or more power, our currents are going up. Things like electromigration need to be addressed. We’re probably going to need more voltage conversion and voltage regulation in the package. That way we can bring higher voltages into the package and then separate them into lower voltages. That means we don’t have to drag as much total current into the package. So power is hitting us in two ways. It’s heat, but it’s also managing that power delivery network electrically. That’s forcing more content into the package, while also doing your best on thermal power dissipation.
Kelly：功耗和用电是巨大的挑战。由于封装级别的集成，它在封装行业中发挥了重要作用。不幸的是，硅会产生大量废热。它的热效率不高。你需要把热量转移到某个地方。我们必须以力所能及的方式参与其中，即芯片和封装边缘之间的事情。对于在最终产品中进行散热的人员来说，无论是手机壳还是数据中心的水冷却器，我们都必须使其具有尽可能高的热效率。我们必须向高性能封装提供多少实际电流也变得有趣。功率没有下降，但电压正在下降。为了提供相同的总功率或更多的功率，我们的电流正在增加。诸如电迁移之类的问题需要解决。我们可能需要在封装中进行更多的电压转换和电压调节。这样我们就可以将更高的电压带入封装中，然后将它们分离成更低的电压。这意味着我们不必将那么多的总电流拖入封装中。因此，权力以两种方式打击我们。它是热量，但它也以电力方式管理电力传输网络。这迫使更多的内容进入封装，同时也尽最大努力降低热功耗。
SE: Any other challenges?
SE：还有其他挑战吗？
Kelly: We’re starting to see a lot of heterogeneous integration designs. We are just at the tip of it. As we go further into that, the intensity to keep pace with what’s required for the end product is also speeding up. You need to be smart about how the heterogeneous technology is invested in. That way, you can cover as many applications as possible. You also need to stay on or above the technical curve so that you can keep up with and challenge your competitors in this aggressive heterogeneous packaging space.
Kelly：我们开始看到很多异构集成设计。我们正处于危机的一角。随着我们进一步研究，满足最终产品需求的强度也在加快。您需要明智地了解如何投资异构技术。这样，您就可以覆盖尽可能多的应用程序。您还需要保持或高于技术曲线，以便您可以在这个竞争激烈的异构封装领域跟上并挑战您的竞争对手。
Fig. 1: Examples of 2.5D packages, high-density fan-out (HDFO), packages with bridges, and chiplets. Source: Amkor
图 1：2.5D 封装、高密度扇出 (HDFO)、桥接封装和小芯片示例。来源：Amkor
SE: Fan-out packaging is gaining steam. In one example of fan-out, a DRAM die is stacked on a processor in a package. What is fan-out packaging and what does it promise?
SE：扇出式封装正在兴起。在扇出的一个示例中，DRAM 芯片堆叠在封装中的处理器上。什么是扇出封装以及它的承诺是什么？
Kelly: When you’re talking about fan-out, it helps to divide it into two parts. There’s low-density fan-out. Then, there’s high-density fan-out, which is a more modern innovation for integrating multiple dies or heterogenous integration. Low-density fan-out has been around for quite some time. It has good electrical properties. It tends to have low layer counts. The package also can be very thin. Low-density fan-out is a good fit for many products, especially mobile. Then there is what I call high-density fan-out. This incorporates the same copper and dielectrics, but we’re imaging them down to finer geometries in terms of lines and spaces. It has multiple layers with tiny vias. High-density fan-out has become a contender for how to integrate small chiplets into bigger modules in this whole heterogeneous universe.
Kelly：当你谈论扇出时，将其分为两部分会有所帮助。有低密度扇出。然后是高密度扇出，这是集成多个芯片或异构集成的更现代的创新。低密度扇出已经存在相当长一段时间了。它具有良好的电性能。它往往具有较低的层数。封装也可以非常薄。低密度扇出非常适合许多产品，尤其是移动产品。然后就是我所说的高密度扇出。它包含相同的铜和电介质，但我们将它们在线条和空间方面成像为更精细的几何形状。它有多层，带有微小的过孔。在整个异构宇宙中，高密度扇出已成为如何将小芯片集成到更大模块中的竞争者。
SE: Fan-out and other packages have redistribution layers (RDLs), which are the tiny metal traces that electrically connect one die to another part of the package. What are the line and space dimensions for the RDLs?
SE：扇出和其他封装具有重新分布层 (RDL)，它们是将一个芯片电连接到封装的另一部分的微小金属迹线。 RDL 的线路和空间尺寸是多少？
Kelly: If you’re talking about high-density fan-out, 2μm line and 2μm space is the sweet spot today. The foundries and OSATs can achieve 2μm-2μm. Once you go below 2μm-2μm or 1.5μm-1.5μm, you are looking at slightly different ways of making the traces. But it’s largely the same dielectrics and copper. A number of companies are working on sub-1μm line/space. Those geometries will be future paths. It comes down to what does a product need. For the next of couple of years, 2μm-2μm is going to be a sweet spot for a lot of products. But as the pitches go beyond 40μm, there will be pressure to add more layers and/or smaller lines, spaces, and vias.
Kelly：如果你谈论的是高密度扇出，2μm 线和 2μm 空间是当今的最佳选择。代工厂和OSAT可以做到2μm-2μm。一旦低于 2μm-2μm 或 1.5μm-1.5μm，您就会发现制作迹线的方法略有不同。但它的电介质和铜基本上是相同的。许多公司正在研究亚 1μm 线/空间。这些几何形状将是未来的路径。这归结于产品需要什么。在接下来的几年里，2μm-2μm 将成为许多产品的最佳选择。但当间距超过 40μm 时，就会面临添加更多层和/或更小的线路、空间和过孔的压力。
SE: Fan-out packages are prone to die shift and warpage. What’s happening here?
SE：扇出封装很容易出现芯片移位和翘曲。这里发生了什么事？
Kelly: In the old days, stress was the bane of your existence in packaging. That’s still there. One of the biggest challenges in new single-die and multi-die packages is warpage. Unfortunately, silicon has a coefficient of thermal expansion of around 2. That’s 2 parts per million of expansion for every degree C that it heats up or cools. All of the organic materials that we use around it are 10 or larger. When they are in intimate contact with one another in a package, and it is heated or cooled, you are expanding and contracting differentially, depending on where you are in the stack. That’s make things move out of plane. There is no such thing as a flat package. It has some sort of warpage or curvature to it. It may not be visible to the eye, but it’s always there. And that adds stress, too. Warpage is something we have to manage. We have good tools for managing it these days. We have a much better materials selection than we did 10 years ago. It’s getting easier to manage warpage for a given size, but the sizes are increasing at the same time. So we are chasing after a moving target.
凯利：在过去，压力是包装行业生存的祸根。那还在那里。新的单芯片和多芯片封装面临的最大挑战之一是翘曲。不幸的是，硅的热膨胀系数约为 2。它加热或冷却每摄氏度，膨胀系数为百万分之二。我们在它周围使用的所有有机材料都是 10 或更大。当它们在一个包装中彼此紧密接触并且被加热或冷却时，您会发生不同程度的膨胀和收缩，具体取决于您在堆叠中的位置。这使得事物移出平面。不存在扁平封装这样的东西。它有某种翘曲或曲率。它可能肉眼看不见，但它始终存在。这也增加了压力。翘曲是我们必须管理的问题。如今我们有很好的工具来管理它。与 10 年前相比，我们的材料选择要好得多。管理给定尺寸的翘曲变得越来越容易，但尺寸同时也在增加。所以我们正在追逐一个移动的目标。
SE: Fan-out packages are now incorporating high-bandwidth memory (HBM). How many HBMs can you incorporate in fan-out?
SE：扇出封装现在集成了高带宽内存 (HBM)。您可以在扇出中合并多少个 HBM？
Kelly: Two or four HBMs are no problem. As you go larger, you have to worry about warpage. You have to worry about moving stress around in the module. The question is, can you manage the warpage? Can you manage the power? Can you keep all of the modulator connects at a pitch that makes sense? Can you manage the high currents and the electromigration? As you get bigger, it’s not a linear increase in the challenges. It’s more of an asymptotic increase.
Kelly：两个或四个 HBM 没问题。当你做得更大时，你必须担心翘曲。您必须担心模块中的压力转移。问题是，你能控制翘曲吗？你能管理电源吗？您能否将所有调制器连接保持在合理的音调上？您能应对高电流和电迁移吗？当你变得更大时，挑战并不是线性增加的。它更像是渐近增长。
SE: What about 2.5D? SE：2.5D 怎么样？
Kelly: 2.5D is the mainstay for high-end AI products, particularly GPUs. That’s a big and growing market. 2.5D is used in data centers to take zettabytes of data and run it against their algorithms to improve the algorithm. When your voice recognition on your phone works better, it’s not because your phone got better. It’s because these high-end, AI GPUs can process more data and the algorithms are better. All of that training takes place in the data center.
Kelly：2.5D是高端AI产品，特别是GPU的支柱。这是一个巨大且不断增长的市场。 2.5D 在数据中心中用于获取泽字节的数据并针对其算法运行它以改进算法。当您手机上的语音识别功能变得更好时，并不是因为您的手机变得更好了。这是因为这些高端人工智能 GPU 可以处理更多数据，算法也更好。所有培训都在数据中心进行。
SE: In 2.5D/3D and other packages, there is a lot of discussion about reticle sizes. What does that mean?
SE：在 2.5D/3D 和其他封装中，有很多关于掩模版尺寸的讨论。这意味着什么？
Kelly: Normally, when people say reticle size, they are talking about a semiconductor fab reticle size. When you talk about 3X or 4X the reticle size in packaging, it’s a terminology for how big the interposer could be. In 2.5D, you could have two or possibly four ASICs. Six HBMs is relatively mainstream. You could see eight, maybe 10 HBMs. It’s going to top out there. It’s not just how many HBMs you’re getting in the package, but it’s also how effective is the package. Maybe you are better off taking that giant 2.5D package and putting it in two packages. Then, you need to find a way to do that and look at all of the system challenges like thermal power and electric power management.
Kelly：通常，当人们说掩模版尺寸时，他们指的是半导体工厂的掩模版尺寸。当您谈论封装中标线尺寸的 3 倍或 4 倍时，这是一个表示中介层尺寸的术语。在 2.5D 中，您可以拥有两个或四个 ASIC。六HBM是比较主流的。您可以看到 8 个，也许 10 个 HBM。它将在那里达到顶峰。重要的不仅仅是您在套餐中获得了多少 HBM，还在于该套餐的有效性。也许您最好将那个巨大的 2.5D 包放入两个包中。然后，您需要找到一种方法来做到这一点，并考虑所有系统挑战，例如热功率和电力管理。
SE: Any other issues with 2.5D?
SE：2.5D 还有其他问题吗？
Kelly: They are large. The interposer itself is a relatively low-tech piece of silicon. It has physical routing on it. And then, if it’s a high-power device, you combine those interposers with embedded capacitors. That helps manage the voltage power deliveries into the chip. The interposer always has been somewhat of a challenge, because finding a source for interposers is difficult. And the interposer availability inside foundries is limited. You can make a lot more money making 5nm chips than you can interposers. Economically, it’s not a good business for a fab. The fab wants to sell high-end silicon. The question is will we ever move from silicon interposers and go into organic interposers for HBM-based products? They are more readily available in the supply chain. Or will we stay with silicon? The jury is still out. For a while, it’s going to be silicon. It’s reliable. It’s robust. These are long-lived products that end customers don’t necessarily want to mess with because they work.
凯莉：它们很大。中介层本身是一块技术含量相对较低的硅片。它上面有物理路由。然后，如果它是高功率设备，您可以将这些中介层与嵌入式电容器结合起来。这有助于管理传输到芯片的电压功率。中介层始终是一个挑战，因为找到中介层的来源很困难。而且代工厂内的中介层可用性有限。制造 5nm 芯片比中介层赚更多的钱。从经济角度来说，这对于晶圆厂来说并不是一个好生意。该晶圆厂希望销售高端硅。问题是我们是否会从硅中介层转向基于 HBM 产品的有机中介层？它们在供应链中更容易获得。或者我们会继续使用硅吗？陪审团还没有定论。有一段时间，它将是硅。这是可靠的。它很坚固。这些是寿命长的产品，最终客户不一定想弄乱，因为它们有效。
SE: Do you envision 2.5D with HBM3 coming out soon?
SE：您预计 2.5D 和 HBM3 很快就会推出吗？
Kelly: People who are on the cutting-edge of AI are already working on getting those products ready.
凯利：处于人工智能前沿的人们已经在努力准备这些产品。
SE: Where do chiplets fit in?
SE：小芯片适合放在哪里？
Kelly: To me, a chiplet is where you take a piece, or pieces, of what was a single SoC and break out some of the functional blocks, or collection of functional blocks, that were originally part of a discrete SoC. Then, the chiplets must be re-integrated at the package level.
Kelly：对我来说，chiplet 是指将单个 SoC 的一个或多个部分分解成一些功能块或功能块的集合，这些功能块最初是离散 SoC 的一部分。然后，必须在封装级别重新集成小芯片。
SE: We’ve seen some companies develop chiplet-like designs using die-to-die interconnects, right?
SE：我们已经看到一些公司使用芯片间互连开发类似小芯片的设计，对吗？
Kelly: There’s two camps here. First, there are companies who are on the leading-edge in this competitive market. You have leaders out there like AMD, Intel and a few others. They have invested heavily in their own die-to-die chiplet bus interfaces. Some of these are proprietary. Those designs have given them a competitive advantage. They are not going to tell the rest of world exactly how they’re doing their chiplet interfaces. They need that advantage in this competitive high-performance marketplace. There is also another camp. There are lots of products that will need to migrate from where they are as an SoC today. Maybe they are a year or several years from that. They also will need chiplets for the same reasons as the others. They need to manage costs in a time-to-market environment with limited engineering resources.
凯利：这里有两个营地。首先，有一些公司在这个竞争激烈的市场中处于领先地位。 AMD、英特尔和其他一些公司都是领先者。他们在自己的芯片到芯片总线接口上投入了大量资金。其中一些是专有的。这些设计给了他们竞争优势。他们不会告诉世界其他地方他们是如何做小芯片接口的。他们需要在这个竞争激烈的高性能市场中获得这种优势。还有另一个营地。现在有很多产品需要从 SoC 的位置进行迁移。也许距离那一天还有一年或几年。出于与其他人相同的原因，他们也需要小芯片。他们需要在工程资源有限的情况下在上市时间环境中管理成本。
SE: The other camp will require several technologies to enable chiplets. For example, to connect one chiplet to another in a package, they will require die-to-die interconnects, right?
SE：另一个阵营需要多种技术来支持小芯片。例如，要将封装中的一个小芯片连接到另一个小芯片，它们将需要芯片到芯片互连，对吧？
Kelly: There are open-source die-to-die technologies from the Open Domain-Specific Architecture (ODSA) sub-project. Multiple companies are working on this together. These technologies are very competitive, meaning they have plenty of bandwidth to support various chiplet architectures. They are flexible enough to support fine pitches, or even larger pitches if it’s an MCM (multi-chip module). Once again, there are going to be two tiers. The top tier is developing their own die-to-die interfaces, which are mostly proprietary. Then you are going to have a growing world that needs chiplets for their own performance, cost, and time-to-market reasons.
Kelly：开放域特定架构 (ODSA) 子项目提供了开源芯片到芯片技术。多家公司正在共同致力于此。这些技术非常有竞争力，这意味着它们有足够的带宽来支持各种小芯片架构。它们足够灵活，可以支持细间距，如果是 MCM（多芯片模块），甚至可以支持更大的间距。再次，将有两层。顶层正在开发自己的芯片间接口，这些接口大多是专有的。然后，您将拥有一个不断发展的世界，出于其自身的性能、成本和上市时间原因，需要小芯片。
SE: In the future, let’s say a company wants to engage with an OSAT to develop a chiplet design using these interfaces. How will this play out?
SE：未来，假设一家公司希望与 OSAT 合作，使用这些接口开发小芯片设计。这将如何进行？
Kelly: The bus selection, the bus qualification and the bus design are always going to reside in the ASIC or processor design community. Down the road, let’s say if a merchant exchange is open enough, people can source physical silicon from a store. Then, you need to get prototypes built, so you go to an OSAT. That might be a business model that you could see in the future. But it’s a lot more complicated than that, because it takes huge simulation capability to make sure things are going to work during your design phase. Our customers now do that, although we have seen a few customers coming to us for more full-service electrical validation of products. That’s a slowly growing trend. I mentioned the two tiers. As that second tier begins to develop more products, we will likely see more of the design cycle moving inside the OSAT.
Kelly：总线选择、总线鉴定和总线设计始终属于 ASIC 或处理器设计社区。未来，假设如果商业交易所足够开放，人们就可以从商店购买物理芯片。然后，您需要构建原型，因此您需要参加 OSAT。这可能是您将来可以看到的商业模式。但它比这复杂得多，因为它需要巨大的模拟能力来确保在设计阶段一切正常。我们的客户现在正在这样做，尽管我们已经看到一些客户向我们寻求更全面的产品电气验证服务。这是一个缓慢增长的趋势。我提到了两层。随着第二梯队开始开发更多产品，我们可能会看到更多的设计周期转移到 OSAT 内部。
SE: What else needs to happen?
SE：还需要发生什么？
Kelly: We are cognizant of these bus types. What we need to understand as an OSAT is what packaging technology is required to wire it up and make it work. Usually it boils down to just a few simple things — bump size, bump pitch, line widths, vias, and maybe layer counts. So we need to understand these buses and how they impact the package. At the end of the day, we’re not actually doing the electrical design, but we’ll see more of that over time. Essentially, the OSAT won’t care whether the die-to-die interface is XSR, AIB, or whatever, as long as you’ve developed what’s going to be needed in advance. It takes a year or two to get significant packaging advances in place and ready.
凯利：我们了解这些巴士类型。作为 OSAT，我们需要了解的是需要什么封装技术来连接它并使其工作。通常它可以归结为一些简单的事情——凸块尺寸、凸块间距、线宽、过孔，也许还有层数。因此，我们需要了解这些总线以及它们如何影响套餐。归根结底，我们实际上并没有进行电气设计，但随着时间的推移我们会看到更多。本质上，OSAT 不会关心芯片间接口是 XSR、AIB 还是其他接口，只要您提前开发了所需的内容即可。需要一两年的时间才能实现重大的包装进步并做好准备。
SE: What about hybrid bonding? Can the OSATs do that?
SE：混合键合怎么样？ OSAT 能做到吗？
Kelly: Definitely. We are getting close to a point where you can buy the technology. And with some investment and your own development, you can get there. So there’s not a huge technical hurdle for an OSAT to do it. It depends on what is a valid business case that would compel an OSAT to get into that business. We are digging deep on understanding the technology.
凯利：当然。我们已经接近可以购买该技术的时刻了。通过一些投资和您自己的发展，您可以实现这一目标。因此，OSAT 做到这一点并不存在巨大的技术障碍。这取决于什么是迫使 OSAT 进入该业务的有效业务案例。我们正在深入了解这项技术。
SE: I assume OSATs like Amkor will continue with bump pitch scaling?
SE：我认为像 Amkor 这样的 OSAT 会继续采用凸点间距缩放吗？
Kelly: You can certainly push your pitch down. We have demonstrated sub-20μm pitches in die-to-die and die-to-wafer with classical copper lead-free bumps. If you’re going below 20μm, or somewhere in between 10μm and 20μm, you’re going to need to move to copper-to-copper hybrid. Managing small pieces of solder caps on tiny little solder bumps has its own distribution of available solder mass. And at some point, those aren’t going to be reliable. We generally push as hard as the customer needs to go, and maybe a little bit further. But somewhere between 20μm and 10μm, customers will jump to the hybrid approach. It has a lot of advantages. The power between the die is low. The electrical signaling path is excellent.
凯利：你当然可以降低你的音调。我们已经展示了采用经典铜无铅凸块的芯片到芯片和芯片到晶圆的 20μm 以下节距。如果要低于 20μm，或介于 10μm 和 20μm 之间，则需要转向铜到铜混合。管理微小焊料凸块上的小块焊料帽有其自己的可用焊料质量分布。在某些时候，这些将不再可靠。我们通常会尽力满足客户的需求，甚至可能更进一步。但在 20μm 到 10μm 之间的某个地方，客户会转向混合方法。它有很多优点。芯片之间的功率较低。电气信号路径非常出色。
SE: Does the packaging industry need new breakthroughs?
SE：包装行业需要新的突破吗？
Kelly: I wish somebody would invent a higher CTE-based silicon. That would help us a lot. If we had lower stress as well as CTEs from different materials that were closer to one another, we would have half the challenges that we have in packaging today. Silicon is complicated. It’s a mixture of high-CTE metals and organic materials with low-CTE bulk silicon. It’s a very non-homogeneous system. You start with this bulk silicon wafer, and then you process practically everything that’s in the stack. So it’s mechanically a little more predictable. If we can come up with material sets where our CTE differences between silicon shrinks, then larger systems will be easier to do. Warpage won’t be as challenging. Stress will be lower. Reliability will be better. And cost targets will be easier to meet.
凯利：我希望有人能发明一种基于更高 CTE 的硅。这对我们有很大帮助。如果我们具有较低的应力以及彼此更接近的不同材料的 CTE，那么我们面临的挑战将是当今包装中的一半。硅很复杂。它是高 CTE 金属和有机材料与低 CTE 块状硅的混合物。这是一个非常非同质的系统。您从块状硅晶圆开始，然后处理堆栈中的几乎所有内容。所以从机制上来说它更容易预测。如果我们能够提出材料组，使硅之间的 CTE 差异缩小，那么更大的系统将更容易实现。翘曲不会那么具有挑战性。压力会更低。可靠性会更好。而且成本目标将更容易实现。
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