Title: Beyond All-Digital PLL for RF and Millimeter-Wave Frequency Synthesis
Abstract: The past several years has seen proliferation of all-digital phase-locked loops (ADPLL) for RF, mm-wave and high-performance frequency synthesis due to their clear benefits of flexibility, reconfigurability, transfer function precision, settling speed, frequency modulation capability, and amenability to integration with digital baseband and application processors. When implemented in nanoscale CMOS, the ADPLL also exhibits advantages of better performance, lower power consumption, lower area and cost over the traditional analog-intensive charge-pump PLL. In a typical ADPLL, a traditional VCO got directly replaced by a digitally controlled oscillator (DCO) for generating an output variable clock, a traditional phase/frequency detector and a charge pump got replaced by a time-to-digital converter (TDC) for detecting phase departures of the variable clock versus the frequency reference (FREF) clock, and an analog loop RC filter got replaced with a digital loop filter. The conversion gAIns of the DCO and TDC circuits are readily estimated and compensated using ‘free’ but powerful digital logic. After covering the fundamentals of ADPLL, the tutorial will venture into the future of RF and mm-wave frequency synthesis: charge-sharing locking (CSL). The idea is that the capacitor of the LC tank itself will be periodically charge-shared with another capacitor charged by a DAC to a voltage that is expected from a waveform at that particular time point, resulting in an instantaneous phase correction. The resulting voltage change will be detected and used to correct the DCO frequency. This results in a great simplification of circuitry and consumed power while delivering sub-100fs integrated jitter.
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