In view of the way in which the density of boards has been increasing in recent years, it is normally very difficult to be able to probe electronic circuits and gain the information that is required to test these boards. As JTAG, boundary scan enables much of a board to be tested with only minimal access, it is now widely used for the test of electronic circuits at all stages of their life. In view of the fact that other forms of test require access either in terms of bed of nails fixtures, while others need to probe a variety of places on the board, boundary scan offers a unique solution to many test requirements.
Although the JTAG, boundary scan technique is aimed at testing circuits, its flexibility enables it to be used for a wide variety of applications including test applications:
While testing remains the major application for boundary scan, it can be see that it is also useful in other applications as well. In view of its flexibility, the technique is widely used, and a powerful tool in both development and production applications.
With the problem of lack of test access to boards starting to become a problem, a group known as the Joint Test Action Group (JTAG) was set up in 1985. Its aim was to address the issues being faced by electronics manufacturers in test strategies and to enable tests to be undertaken where no other technologies could gain access.
The introduction of surface mount technology and further miniaturisation had meant that people feared access to boards for testing would be severely limited. To overcome this, new strategies would be required.
The original goal for boundary scan was to complement existing techniques including in-circuit test, functional built in test and other techniques and to provide a standard that would enable the testing digital, analogue and mixed signal circuits.
The standard for boundary scan that was devised has been adopted by the Institute or Electrical and Electronics Engineers, IEEE in the USA as IEEE 1149. The first issue of the standard, IEEE 1149, was in 1990. The stated purpose of IEEE 1149 was to test the interconnections between integrated circuits mounted on boards, modules, hybrids and other substrates. As most of the problems occurring with electronics circuits occur with the interconnections, the IEEE 1149 test strategy would reveal most of the problems.
In 1993, a revised version of the boundary scan, IEEE 1149 standard was issued which contained many clarifications, enhancements and corrections. Then in 1994, a further issue of the IEEE 1149 standard took place. This introduced the Boundary Scan Description Language, BSDL. This enabled boundary scan tests to be written in a common language, thereby improving the way in which tests could be written and code re-used, thereby saving development time.
The JTAG, boundary scan test technique uses a shift register latch cell built into each external connection of every boundary scan compatible device. One boundary scan cell is included in the integrated circuit line adjacent to each I/O pin, and when used in the shift register mode it can transfer data along to the next cell in the device. There are defined entry and exit points for the data to enter and exit the device, and it is therefore possible to chain several devices together.
Under normal operating conditions the cell is set so that it has no effect and it becomes invisible. However when the device is set to test mode, it permits a serial data stream (test vector) to be passed from one shift register latch cell to the next. Boundary-scan cells in a device can capture data from integrated circuit line, or force data onto them. In this way a test system that can input a data stream to the shift register chain can set up states on the board, and also monitor data. By setting up one serial data stream, latching this into place, and then monitor the returning data stream, it is possible to gain access to the circuits on the board and check that a returning data stream is what is expected. If it is, then the test can pass, but if not the boundary scan system has detected and problem that can be further investigated.
There are a number of JTAG control and data lines that form the test access port, TAP. These lines known as TCK, TMS and the optional TRST line are connected in parallel to the chips in the boundary scan chain. Connections designated TDI (input) and TDO (output) are daisy chained together to provide a path around the boundary scan chips for the data. Data is sent into the TDI of the first chip, and then TDO from the first chip is connected to TDI of the next and so forth. Finally the data is taken from the TDO of the last IC in the daisy chain.
JTAG, boundary scan is an ideal test tool for use in many applications. The most obvious applications for boundary scan are within the production environment. Here the boards can be tested and problems that might otherwise go un-detected because of lack of test access can be adequately tested. In fact boundary scan technology is being combined with other technologies to provide what is termed a combinational tester.
In addition to being used in production test, boundary scan, JTAG, IEEE 1149, can also be used in a variety of other test scenarios, including product development and debugging as well as field service. This means that the boundary scan code can be re-used for test areas, and hence the cost can be split over these applications. Not only does this indicate that boundary scan is a powerful tool, but it also makes it financially attractive.
One of the chief costs for any development these days is the cost of the software, and this is particularly true for boundary scan where there is little hardware. This means that any savings that can be made in the time taken for the software development can significantly reduce the costs. Accordingly a Test Programme Generator (TPG) is an integral part of a boundary scan system.
Typically the test programme generator requires the net-list of the Unit Under Test (UUT) and the Boundary Scan Description Language (BSDL) files of the boundary scan components contained within the circuit. With this information it is possible for the test programme generator to create the test patterns used for the test. These allow the system to detect and isolate any faults for all boundary-scan testable nets within the circuit. It is also possible for the test programme generator to create test vectors that enable the system to detect faults on the nodes or pins components non-boundary scan components that are surrounded by boundary scan devices
JTAG, boundary scan, IEEE 1149 is a test technique that is now well established. Although it requires test programmes to be generated before it can be used, it nevertheless provides a very cost effective method of gaining access for test vectors into an electronic circuit board. With circuit board real estate being at a premium, the cost of adding probe or access points for other type of electronic test technologies would be prohibitive, if indeed it were possible. Accordingly boundary scan provides a solution to many test problems at a cost that can be amortised over several test arenas from development through production test to field test. In all of these environments, boundary scan provides an effective solution, both in terms of performance and cost.
Boundary scan is now a well established test technology. Boundary scan has been in use since the early 1990s when the Joint Test Action Group (JTAG) devised a solution to testing the many new boards that were being developed and manufactured where there was little access for test. With boundary scan established, a further step was to develop a standard language that could be used in the creation of boundary scan tests. With this, the boundary scan development language was created.
The Boundary Scan Description Language, BSDL, has been designed as the standard programming language for boundary scan devices that comply with IEEE 1149.1-1990, and the intention that it should be used by boundary scan test developers, device manufacturers, ASIC designers, ATE manufacturers and anyone using boundary scan. The aim is that BSDL will promote consistency throughout the electronics industry. Additionally, it will enable the specification of any boundary scan functions on a device in a more useful and consistent manner.
The Boundary Scan Description Language came out of the development of the boundary scan test philosophy. The initial IEE 1149.1 standard describing boundary scan was approved and released in 1990, and as a result the use of boundary scan techniques started to grow. The next revision of the standard occurred in 1993, but in 1994 another revision occurred, and this incorporated the Boundary Scan Description Language.
The Boundary Scan Description Language enables users to provide a description of the way in which boundary scan applies to different devices. As each user will tend to apply the boundary scan standard in a slightly different way, it is necessary to express tests in a comprehensible, specific and usable fashion.
BSDL is written within a subset of VHDL. VHDL or VHSIC Hardware Description Language, is commonly used as a design-entry language for FPGAs and ASICs in electronic design automation of digital circuits, and as such it is ideal for work with boundary scan because design of many chips is performed using this language. However BSDL is a "subset and standard practice" of VHDL, i.e. the scope of VHDL is limited for this application.
During the design of BSDL there were two main criteria for the language:
BDSL enables accurate and useful descriptions of the features of a device that uses boundary scan. The language can be used by the boundary scan tools to make use of the device features to enable test programme generation, failure diagnosis as well as being used in any testability analysis.
Although the Boundary Scan Description Language, BSDL, is not a language that can be sued for hardware descriptions, but a language that can be used to define the data transport characteristics of the device, i.e. how it captures, shifts, and updates data. This is then used in defining the test capability.
The BSDL file includes the following data:
The Boundary Scan Description Language, BSDL, is widely used within the JTAG, boundary scan community to enable consistent, accurate and useful information to be defined for a boundary scan enabled device. In this way, the chip can be incorporated into a design, and its capabilities used to their full in the most efficient manner.
Boundary scan, or as it is also termed JTAG is a powerful test technology that can be used to test today's highly complex and compact printed circuit assemblies. Boundary scan provides a highly effective means of testing circuits where access is not possible or convenient using other test technologies. It is found that the access required for techniques such as In-Circuit Test and Functional ATE is often not sufficient to enable a satisfactory test of the whole circuit to be undertaken. However JTAG, boundary scan is able to provide a comprehensive test of many circuits provided that the circuit is designed to enable JTAG, boundary scan techniques to be used.
JTAG, boundary scan is defined under IEEE 1149.1 which describes a four wire serial interface (a fifth wire may be used but is optional) for testing printed circuit boards and integrated circuits where access is limited. It is widely used on VLSI chips such as microprocessors, DSP chips, FPGAs and the like. These integrated circuits have boundary scan shift registers incorporated along with a state machine that enable testing to be accomplished without the need to physically access every node on the board or device. In this way boundary scan is an ideal test technology for many of today's test scenarios.
When designing a circuit that can use JTAG, boundary scan test techniques, there are some items that are mandatory, while others make the testing more effective or easier to accommodate. However incorporating as many techniques as possible into the design will enable the best test to be undertaken, and the most problems found, either during the development phase of the product, or during production or field test.
In any design the choice of components can have a major impact on the overall concept for the item. This is true when considering using boundary scan / JTAG techniques for testing a printed circuit board. It is important that the components that are included in the circuit that will be tested using boundary scan are chosen to accommodate testing using this methodology.
Once the required components have been chosen, it is necessary to ensure that the design for the circuit enables easy testing, and maximum access when using boundary scan / JTAG. There are a number of techniques available to ensure that the maximum use can be made of IEEE 1149.1.
One important aspect associated with any form of electronics test, and this includes JTAG, boundary scan is that of test access. This is obviously important in terms of choosing components and designing the circuit correctly. However physical access is equally important. To ensure that circuits can be tested easily, many boards include a JTAG connector specifically for test. This JTAG connector can be a very low cost item as it only needs to be used during the production and test phases of the product. However good reliable test access is very important. The JTAG connector can save time, especially if it provides very reliable performance where other methods may not be so reliable. Poor reliability can lead to many house of lost time fault finding problems associated only with the test access. In view of this and the ease of performing tests, a JTAG connector can be a cost effective addition to a board in many cases. A JTAG connector should therefore be considered as one of the design considerations at the earliest part of the design phase of a product.
This is not an exhaustive summary of all the precautions to take when designing a circuit board that will use JTAG, boundary scan. However it gives a useful guide to some of the basics that may be employed.
JTAG, boundary scan is now a well established technology which is widely used in many areas of test within the electronics industry. The use of JTAG technology arose out of the need to be able to provide sufficient test access for every more complex boards while test access was reducing. As a result boundary scan technology was introduced and the JTAG spec or JTAG standard is now firmly established.
With the increase in complexity of electronics items in recent years, the JTAG spec has become the accepted test format for testing compact and complicated electronics units. In fact JTAG is often the only practicable method that can be used in many instances as access to many circuit nodes is not possible.
JTAG technology uses a technique that does not require the test system to have direct access to each node. The JTAG standard is able access the state of nodes within the circuit by passing a serial data stream into the item under test, and then reading the status of the stream as it exits the board.
To achieve this, the JTAG specification defines a shift register latch cell that is built into each external connection of every boundary scan or JTAG compatible device. Under normal operating conditions, i.e. when not being tested the cell remains transparent and does not affect the operation of the device. When used for boundary scan, JTAG testing the shift register is set to a mode where it can transfer data along to the next cell in the device. There are defined entry and exit points for the data to enter and exit the device, and it is therefore possible to chain several devices together. In this way boundary scan, JTAG can test individual ICs or complete boards (provided there are sufficient JTAG, boundary scan compatible devices on the board.)
When being used in JTAG, boundary scan test mode, it permits a serial data stream (test vector) to be passed from one shift register latch cell to the next. The boundary-scan cells in the devices capture data from integrated circuit line, or force data onto them. In this way a test system that can input a data stream to the shift register chain can set up states on the board, and also monitor data. By setting up one serial data stream, latching this into place, and then monitor the returning data stream, it is possible to gain access to the circuits on the board and check that a returning data stream is what is expected.
The development of boundary scan, JTAG technology started in 1985 when a group known as the Joint Test Action Group was set up. The initials for this group were soon shortened to JTAG and the name has since remained to describe this technology which is now firmly established.
The resulting solution devised by JTAG was the boundary scan technology for test. The resulting JTAG specification has since been widely used by many areas of the electronics industry, becoming a standard technique used by many manufacturers
Boundary scan, JTAG technology relies on using VLSI integrated circuits that have a boundary scan capability. As a result there is a need for standardisation across the electronics industry. In order to ensure this occurred, boundary scan was adopted by the Institute or Electrical and Electronics Engineers, IEEE in the USA as IEEE1149. The first issue of the boundary scan standard was released in 1990 and its stated purpose was to test the interconnections between integrated circuits mounted on boards, modules, hybrids and other substrates. Since then further revisions of the JTAG specification have taken place.
In view of the importance of the JTAG spec, and its use by many manufacturers, test equipment vendors and others the specification has been adopted by the IEEE, Institute of Electrical and Electronic Engineers based in the USA.
If copies of the IEEE 1149.1 standard are required, they may be obtained from the following source:
IEEE Standards Department445 Hoes Lane
P.O. Box 1331
Piscataway, NJ 08855-1331
USA
In order to adopt the boundary scan, or JTAG test solution, the IEEE set up a number of committees or working groups to address the different aspects of the technology, and the resulting standards bear their numbers. In fact, Joint Test Action Group or JTAG is the usual name used for the IEEE 1149.1 standard entitled Standard Test Access Port and Boundary-Scan Architecture. The IEEE 1149 standard numbers are the ones that are quoted as the definitions for JTAG technology.
The committee numbers are given below:
Although IEEE 1149.1 is the most commonly used standard, i.e. the JTAG specification and it is often seen quoted in the literature, the others are also important in their own areas. As can be seen from the list, some groups working on different or allied aspects of the JTAG specification have completed their tasks and they have been merged or made obsolete.
The JTAG specification as defined under the IEEE 1149.1 standard is the one that is used by the electronics test industry. It is widely used because it enables a much greater test coverage to be achieved than any other test technology, especially for assemblies where access to nodes is not possible. As a result the JTAG specification is used for testing items from individual integrated circuits up to complex electronics assemblies. In view of the fact that there are no other viable test technologies available for these circumstances, the JTAG specification will be in evidence for many years to come
In order to be able to use the boundary scan, JTAG system it is necessary to be able to communicate correctly with any board that is set up to use JTAG. The JTAG interface has a number of lines that are used and together these are collectively known as the Test Access Port, TAP. This JTAG port is used for JTAG control as well as providing connections by which the serial data may enter and leave the board.
On some items of electronics equipment there may be a specific JTAG connector or interface into which a JTAG tester may be connected. This approach is particularly useful for any field test that be required as the item under test can be accessed without the need for complete disassembly of the unit.
For most units there is no specific JTAG connector. Instead the connections to the JTAG interface are routed via the main connector to the assembly. These connections would not always be used for the main operation of the unit unless the JTAG test is required as part of the Built in Self Test, BIST where the JTAG controller is located externally to this board or assembly.
There is a maximum of five lines that may be used for a JTAG interface, although one of them is optional and therefore may not always be present. This may be the case when the design becomes short of pins on a connector and the optional one can be sacrificed.
The signals that may be used are given below:
As seen above, the JTAG connections are implemented on the board by daisy chaining devices residing on the JTAG bus i.e. one to the next and so forth in a serial fashion. The TDO pin of one device connects to the TDI pin of the next device. In some instances there may be more than one JTAG connector.
The JTAG interface is generally an integral part of any electronics assembly. While some items of equipment may provide a specific JTAG port for field test, this is not always the case. In these cases the JTAG interface may accessible via the main assembly connector for which there are a few dedicated pins used for JTAG boundary scan testing. The pins that make up the JTAG interface would not be used under normal operational circumstances.
In addition to the standardised JTAG connections defined above, the JTAG interface may also be expanded to provide additional functionality for debug. Many chip manufacturers have their own proprietary additional connections that work together with the basic JTAG signals to provide a considerable degree of additional functionality.
These additional lines are generally vendor specific, although a new standard known as IJTAG defined under IEEE 1687 provides standardisation to the additional lines and functionality.
There is no standard for the connector type that should be used for the JTAG connection. Different vendors use different JTAG connector types, often in the form of headers. Different types may also be used between development and production, and in some cases multiple headers may be incorporated to enable different tool support. On some production boards, test points or connections within existing connectors may be used.
There are some common points which are tabulated below:
| Parameter | Details |
|---|---|
| Connection pitch | 0.1 inch (2.54 mm) pin spacing, or occasionally edge connector. |
| Connector mechanicals | Shrouded header recommended to prevent incorrect insertion. |
| Noise immunity | Good practice to ground every other pin. |
When connecting to the JTAG interface, care must be taken to keep leads and internal PCB links as short as possible to preserve the signal integrity and timing.
The IEEE 1149.1, JTAG standard for boundary scan testing has been in existence for many years and it is now well established. Boundary scn testing ahs revolutionished However there are some limitations to this form of testing. In particular IEEE 1149.1 does not address AC coupled signals or differential nets. In order to address these shortfalls, a new committee was set up to develop a new standard to address these problems. Known as IEEE 1149.6, the new specification adds additional functionality to the boundary scan test technique, allowing it to be used in additional circumstances.
In their brief the IEEE indicated they were well aware that the existing boundary scan IEEE 1149.1 or JTAG standard did not address some of the newer digital network topologies such as AC coupled differential connections on very high speed digital paths (i.e. more than 1 GBps). The original IEEE 1149.1 boundary scan structures and methods were intended to test DC coupled single ended networks since the AC coupling blocks any static signals.
In addition to this, differential networks are also inadequately tested. To achieve the testing of differential networks it is necessary to insert boundary cells between the differential driver or receiver and the chip pads, or insert boundary cells before the differential driver or after a differential receiver. Neither of these solutions is particularly acceptable because it may degrade the performance or the testing.
In addition to this the IEEE 1149.4 methods that are intended for testing analogue circuits do not naturally lend themselves to testing the very high speeds encountered in the high speed AC coupled differential networks. Often the methods required for analogue testing are too intrusive for these digital networks and it can have an impact on the pin count.
Accordingly the aim of IEEE 1149.6 was to define a standard that was robust, and provided a greater test and diagnostic capability than previous methods yet required minimally intrusive structures and test methods. The project was aimed at addressing the physical interface as well as the protocols and any changes to software and BSDL.
The IEEE 1149.6 standard was initially released in March 2003, and its use has grown since then as a result of the capabilities it offers.
The IEE 1149.7 standard is a new standard also referred to as Compact JTAG or cJTAG that has been developed to meet the ever increasing needs of testing modern electronics boards and systems. The original JTAG standard provided a real leap forwards in testing, but as many designs moved away from conventional printed circuit boards to multi-chip modules, stacked die packages,and further testing and debug was required, including under power down and low power operation, an addition to the original JTAG standard was needed.
The resulting IEEE 1149.7 standard builds on the existing JTAG standard to meet many of the new requirements. The new IEEE 1149.7 standard does not replace the older IEEE 1149.1 JTAG standard, but its aim is to enable this basic JTAG test technique to be used in many of the new high density boards where greater flexibility and further functionality is required to provide sufficient test coverage. These additional facilities are available on Compact JTAG / IEEE 1149.7 while still providing backwards compatibility.
Equipment conforming to the IEEE 1149.7 cJTAG or Compact JTAG standard is now available from a variety of vendors and it is anticipated that its use will greatly increase over the coming years.
One of the key elements of Compact JTAG is that the IEEE 1149.7 standard defines a new Test Access Port (TAP) known as TAP.7. This extends the functionality of the Test Access Port of the original JTAG standard (TAP.1) in several ways.
One of the main elements is that the focus of JTAG testing has been broadened somewhat. The original IEEE 1149.1 standard was developed as a means of testing board level interconnections, but the new IEEE 1149.7 standard incorporates additional features to bring additional test facilities. It provides power management facilities; supports increased chip integration; application debug; and device programming.
In view of the fact that not all facilities will be required for all testers and applications, the IEEE 1149.7 features are grouped into six classes which are progressively graded. Each class is a superset of all the lower classes. Classes T0 to T3 extend the original IEEE 1149.1 standard and enable greater functionality. Classes T4 and T5 are focussed on the two pin system operation rather than the four required for the original JTAG system.
| cJTAG Class | Details |
|---|---|
| Class T0 | This is the basic class for Compact JTAG testing. It maintains strict compliance to the original IEEE 1149.1 but in addition to this it also allows multiple Test Access Ports on a single chip. |
| Class T1 | This class provides the class 0 facilities as well as providing support for the 1149.7 command protocol, the generation of functional and test resets, and power control. |
| Class T2 | The Class 2 functionality additionally provides the ability to bypass the system test logic on each IC. This results in a 1-bit path being created for Instruction Register and Data Register scans. |
| Class T3 | This class adds the facility to use TAP.7 controllers in a 4-wire star topology. |
| Class T4 | This class adds support for advanced scan protocols and 2-pin operation where all the signalling is accomplished using only the TMS and TCK pins. The TDO and TDI lines can be removed if required. |
| Class T5 | Class 5 provides the maximum functionality within IEEE 1149.7. It adds support for up to 2 data channels for non-scan data transfers. These can be used for application specific debug and instrumentation applications. |
Although the Compact JTAG or cJTAG standard specified under IEEE 1149.7 only uses two pins for the TAP rather than the four pins used for the original IEEE 1149.1 standard, it is still able to provide additional functionality. These enhancements enable System on Chip pin counts to be reduced and it provides a standardised format for power saving operating conditions. As a result, the IEEE 1149.7 standard will enable JTAG style testing to be undertaken on many new designs more easily than it would have been possible using the older IEEE 1149.1 standard.
IEEE 1687 is a proposed IEEE Standard for the access and operation of embedded instruments. It is also referred to by the name IJTAG or Internal JTAG.
The new IJTAG standard will enable a far greater degree of internal test to be accomplished, and with the level of intellectual property, IP being incorporated into ASICs and FPGAs, etc, this is a growing issue.
As boundary scan, defined under IEEE 1149.1 became better established, the capabilities of the JTAG test access port, TAP, interface were explored. The interface allowed for a much greater level of access into the core of circuits and chips themselves without the need for intrusive access.
The development of IJTAG has come about to a large degree because of the growing level of functionality within each silicon chip or die. These days, manufacturers do not just use their own IP on the chip, but also that bought in from other specialists.
Even though the different functional modules within the overall die have their operation and interfaces specified, there is still a great need for integration testing, even if many simulations have been performed. This testing is not always easy to achieve because access to a die is obviously difficult.
To overcome this issue, on board test instruments can be incorporated into the system and the boundary scan JTAG interface used to access them and control them.
To ensure the greatest level of functionality the new IJTAG system defined by IEEE 1687 provides additional access and functionality over that which could be obtained from the basic JTAG TAP.
IJTAG uses the JTAG TAP as the primary interface, but extends the operation considerably. One of the key features is that it standardises the interface for embedded instruments, along with the description of their operation, and connectivity through the design hierarchy.
IJTAG is simple to implement and use because of the plug-and-play approach for both in-house and third party elements.
The key advantages and elements of the IJTAG system are summarised in the table below:
| Parameter | JTAG | IJTAG |
|---|---|---|
| External interface to internal elements. | Instrumentation control is vendor specific. | Standardised and with plug-and-play capability. |
| Internal control. | Ad-hoc and typically vendor specific. | Standard protocol. |
| Instrument access. | manually defined at the JTAG TAP interface. | Automated re-targeting from IJTAG TAP to instrument through a logical hierarchical structure. |
| Register size | Fixed for each instruction. | Variable. |
Two elements of the IJTAG interface that are key to its operation.
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