Sigma delta A/D converters (ΣΔ-ADC) combine over sampling analog sigma delta modulators with digital decimation filters to achieve high precision and cost effective A/D conversion solutions. ΣΔ-ADCs are used to implement high-precision, low-power A/D converters for applications such as sensor interfaces and audio processing. Until recently a delta sigma solution needing mixed signal circuits has required full-custom ASIC design. New design techniques incorporating via-configurable array (VCA) technology allow mixed signal IP such as ΣΔ converters to be created and reused as soft-IP.
Analog to digital conversion (ADC) is the process of sampling a continuous analog signal and converting the signal into a quantitized representation of the signal in the digital domain. Many different ADC architectures are available to convert analog signals into digital representations. The conventional ADC process transforms an analog input signal x(t) into a sequence of digital codes x(n) at a sampling rate of fS = 1/T, where T denotes the sampling interval. The sampling function is equivalent to modulating the input signal by a set of carrier signals having frequencies of 0, fS, 2fS, 3fS,…, see Figure 1. The sampled signal may be expressed as the summation of the original signal component and the signal?s frequency modulated by integer multiples of the sampling frequency. Therefore, any signal components about the Nyquist frequency in the input signal cannot be properly sampled and such signals in fact will get ?folded? into the base-band signal creating artifacts in the sampled signal which were not present in the original input signal. This non-linear ?folding? or signal distortion is referred to as aliasing. Anti-aliasing filters are therefore required to prevent or reduce these aliasing artifacts. Many A/D converters such as successive approximation register (SAR) and flash converters operate at the Nyquist rate (fN). These converters typically sample the analog signal at a sample frequency (fS) approximately twice the maximum frequency of the input signal. A Nyquist rate ADC converts the analog signal into an n-bit representation at every Nyquist sample time. Since the Nyquist rate may only be approximately 2x the frequency of the sample pass band of interest a high-performance low pass filter (anti-aliasing filter) is required to limit the maximum frequency components input to the A/D converter.
Figure 1 – Analog and Sampled Signals with Aliasing
Sigma delta A/D converters do not instantly digitize the incoming analog signal into a digital sample of n-bit precision at the Nyquist rate. Instead, a sigma delta ADC over samples the analog signal by an over sample ratio of (N) resulting in fN << fS (over sample rates of 16, 32, 64, 128 are common). The over sampling A/D conversion is performed at a lower precision (coarser quantization). In fact, many ΣΔ-ADC are effectively a 1-bit A/D. As shown in Figure 2, the output of the modulator or 1-bit A/D is a bit stream with the one?s density of the stream proportional to the magnitude of the sine-wave input. This 1-bit A/D stream that is generated at N*fS (Over Sampling Rate * NyQuist Rate) can be digitally filtered and decimated back down to a Nyquist rate of n-bit precision samples.
Figure 2 – ΣΔ modulator output representing sine-wave input
The 1-bit A/D stream is digitally filtered to obtain an n-bit representation of the analog input. In simplified terms the 1-bit A/D stream is accumulated over (N) sampling cycles and divided by (N). This yields a decimated value which is the average value of bit stream from the modulator as shown in Figure 3.
Figure 3 – ΣΔ A/D stream accumulated and decimated to represent an n-bit value of the input
In addition to anti-aliasing, a Nyquist rate ADC also requires a precise sample and hold analog circuit. The circuit holds continuous amplitude, discrete time samples of the analog waveform stable while the converter performs the quantization. The sample and hold output is compared to a set of reference levels within the ADC. The quality and precision of these reference levels is a limiting factor for high resolution A/D converters. For example, a 16-bit Nyquist rate ADC requires 216 ? 1 (65535 different reference levels). A typical converter may span a 2V input range. The spacing between any two reference levels is only 30 μV. This type of matching is difficult to achieve on an integrated circuit without the use of expensive and complicated trimming techniques.
One of the major advantages of a ΣΔ-ADC over a conventional parallel or Nyquist ADC is the relaxation of the requirements for the anti-aliasing filter. As mentioned above, the requirements of an anti-aliasing filter for a Nyquist rate ADC require a sharp transition from the pass band (fB) to stop band (fN) as shown in . The anti-aliasing filter for a conventional ADC needs to be flat through the pass band and attenuate signals above the stop band by an attenuation factor greater than the dynamic range of the ADC.
Figure 4 – Transition band for Nyquist and over sampled converters
An over sampling A/D converter moves the sampling frequency (fS) much farther away from the Nyquist frequency than a Nyquist rate converter by a factor of (N). Since the complexity of an anti-aliasing filter is highly proportional to the ratio of the width of the transition band to the width of the pass band, over sampled converters require far simpler anti-aliasing filters than Nyquist rate converters with similar performance. What may have been a complex filter requiring significant component matching for a Nyquist rate converter may be replaced by a simple R-C filter in an over sampled converter.
A ΣΔ A/D converter is a mixed signal design consisting of an analog ΣΔ modulator followed by a digital filter as shown in Figure 5. This implementation shown here is a fully differential second order modulator followed by a Sinc3 decimation filter.
Figure 5 – High-level view of delta-sigma modulator
For analysis purposes a second order delta sigma modulator can be represented by the block diagram of Figure 6.
Figure 6 Block diagram of a second order ΣΔ modulator
The first summation and function H1(z) represents the first integrator, the second summation and function H2(z) represents the second integrator, and the third summer represents the comparator, where QN(z) is the quantization noise generated by the comparator. Note the one-bit DAC in the feedback loop is considered ideal and is not shown in Figure 6. That is to say when the output of the modulator is a logic one, the output of the DAC is a positive reference voltage while the opposite occurs when the output of the modulator is a logic zero. Analysis of the block diagram yields the transfer function for the modulator as shown in Equation 1.
IN(z) is the input signal, H1(z) and H2(z) are the integrator transfer functions, QN(z) is the quantization noise generated by the comparator, and OUT(z) is the modulator output. The block diagram shows the summers in the integrators output the difference between the output signal and the input to each integrator (Δ), while the H(z) functions are chosen so they sum (accumulate) these differences (Σ). This functionality permits the average input to match the average output. For example, given a sinusoidal input whose peak to peak amplitude is near the maximum allowable peak to peak amplitude of the modulator; when the input is at its maximum positive peak the output of the modulator should be nearly all logic ones. As the signal passes through the mid-point of the wave the modulator output should be an even mix of logic ones and zeroes. Finally, as the sinusoidal input is at its minimum peak the modulator output should be nearly all logic zeroes.
The schematic for a second order ΣΔ modulator is shown in Figure 7 and is constructed of two switched capacitor integrators, a clocked comparator, a 1-bit digital to analog converter and a non-overlapping clock generator. The schematic is targeted to primitives on a via configurable array (VCA) platform developed by Triad Semiconductor. VCA platforms contain pre-diffused analog and digital resources that are interconnected by placing vias in a global routing fabric.
Figure 7 – Differential 2nd order ΣΔ modulator implemented with VCA primitives
As mentioned above, the H(z) transfer functions must be selected so the average input equals the average output. To accomplish this, the first integrator was chosen to be a delay free, parasitic insensitive integrator whose half circuit transfer function is shown in Equation 2.
In this implementation C1 is 4 pF and C2 is 2 pF. This gives a gain of one-half. The second integrator is a parasitic insensitive integrator whose transfer function is shown in Equation 3.
As with the first integrator, C1 is 4 pF and C2 is 2 pF, thus giving a gain of one-half. The gains for the integrators are set in this fashion to ensure the integrators do not saturate. Also to help avoid saturation, the amplifiers used in the integrators have rail-to-rail output swing capability. The clocked comparator acts as the 1-bit quantizer and consists of an amplifier whose output is connected to the D input of a flip flop. The output of the flip flop (Q) is a logic one when the voltage between the non-inverting input and the inverting input (also, non-inverting output and inverting output of the second integrator respectively) is positive and is a logic zero when the voltage is negative. The output of the comparator (also the output of the modulator) controls the one-bit DAC in the feedback path. The one-bit DAC consists of transmission gates that determine the polarity of a reference voltage to be summed with the inputs of the integrators. For the first integrator, when the output of the modulator is a logic one, the non-inverting input is summed with the negative reference voltage. Conversely, the inverting input of the first integrator is summed with the positive reference voltage when the modulator output is a logic one. The polarity of the input and the polarity of the reference voltage do not match (i.e., the non-inverting input is summed with the inverting reference when the modulator output is a logic one) for the first integrator because its transfer function is inverting. This is required for the ΣΔ modulator to be stable. For the second integrator the polarity of the reference voltage matches the polarity of the input. Substitution of Equation 2 and Equation 3 into Equation 1 results in Equation 4.
Equation 4 reveals the input signal is merely delayed whereas the quantization noise is moved to higher frequencies by a second-order differential function. The shifting of quantization noise to higher frequencies is why ΣΔ modulators are also referred to as noise shaping modulators. Provided the frequency of the input signal is low relative to the sample rate of the ΣΔ modulator, and a digital low pass filter is used, the quantization noise is greatly reduced. The quantization noise can be reduced further by increasing the order of the modulator at the expense of complexity and increased component count. Also, it has been shown for an analog to digital converter employing the second order modulator discussed here, the ideal signal to noise ratio for a sinusoid is given by Equation 5.
Here fsignal is the highest frequency of interest in the input signal and fsample is the sample rate (clock frequency for the ΣΔ modulator.) The sample frequency divided by the input signal frequency is known as the over sampling ratio. Inspection of Equation 5 shows with every doubling of the over sampling ratio the ideal signal to noise ratio increases by 15 dB.
The performance of the ΣΔ modulator can be quantified by collecting output data using a sinusoidal input source over several seconds. It is necessary to collect data for a long period of time (3 to 5 seconds) to attain good low frequency resolution. Also it should be noted, the signal source must have an SNR greater than the resolution of the A/D. This data can then be post processed with an FFT to view the signal in the frequency domain as shown in Figure 8. In this case the input signal frequency is 100 Hz and the ΣΔ modulator sample rate is 500 kS/s. Notice the noise floor is more than 100 dB below the maximum amplitude of the input signal (with the exception of some harmonics due to the signal generator) up to approximately 3 kHz. In other words, this ΣΔ modulator is suitable for realization of a 16 bit A/D for an over-sampling ratio of 500/3 = 167 which approximately concurs with Equation 5.
Figure 8 – 2nd order ΣΔ modulator spectral plot for sinusoidal input.
The over-sampled output of the ΣΔ modulator is processed by the digital filter shown in Figure 9. The decimation filter consists of a 3 stage accumulator that serves as a Sinc3 filter followed by a 3 stage differentiator decimator circuit.
Figure 9 – Sinc3 digital decimation filter
The DSM_IN 1-bit input stream is accumulated and decimated to create a 16-bit data word that is output at the ADC Nyquist word rate. The filter is implemented as Verilog RTL code as shown below.
// decimation.v // Decimation filter with Sinc3 filter followed by // Differentiator and Decimation // module decimation( DSM_i, DSM_clk_i, WordClk_i; Reset_i, DWord_ro); input DSM_clk_i; // DSM-rate clock (bit clock) input WordClk_i; // Output Word-rate clock input Reset_i; // Active-hi reset input DSM_i; // Input from Modulator output [15:0] DWord_ro; // 16-bit Output Word reg [23:0] Acc1_r; reg [23:0] Acc2_r; reg [23:0] Acc3_r; reg [23:0] Acc3_q1_r; reg [23:0] Acc3_q2_r; reg [23:0] Diff1_r; reg [23:0] Diff2_r; reg [23:0] Diff3_r; reg [23:0] Diff1_q1_r; reg [23:0] Diff2_q2_r; reg [15:0] DWord_ro; // // Internal Wires // // 2’s-comp version of DWord wire [23:0] DWord_2comp_w; // Sinc Filter assign DWord_2comp_w = (DSM_i==1’b0) ? 24’d0 : 24’d1; // Accumulator (Integrator) always @(negedge DSM_clk_i or posedge Reset_i) if (Reset_i) begin /* initialize acc registers on Reset_i */ Acc1_r <= 24’d0; Acc2_r <= 24’d0; Acc3_r <= 24’d0; end else begin /* perform accumulation process */ Acc1_r <= Acc1_r + DWord_2comp_w; Acc2_r <= Acc2_r + Acc1_r; Acc3_r <= Acc3_r + Acc2_r; end // // Decimation Filter // /* Decimation stage (MClkOut/ WordClk) */ always a(negedge DSM_clk_i or posedge Reset_i) if (Reset_i) word_count <= 8’d0; else word_count <= word_count + 8’d1; // // Differentiator and Decimation // always @ (posedge WordClk_i or posedge Reset_i) if(Reset_i) begin Acc3_r_d2 <= 24’d0; Diff1_q1_r <= 24’d0; Diff2_q1_r <= 24’d0; Diff1_r <= 24’d0; Diff2_r <= 24’d0; Diff3_r <= 24’d0; end else begin Diff1_r <= Acc3_r – Acc3_q2_r; Diff2_r <= Diff1_r – Diff1_q1_r; Diff3_r <= Diff2_r – Diff2_q1_r; Acc3_q2_r <= Acc3_r; Diff1_q1_r <= Diff1_r; Diff2_q1_r <= Diff2_r; DWord_ro <= Diff3_r[23:8]; end endmodule |
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