Part2
The Clock Tree Optimization (CTO) Options To Reduce Skew
Question:
What are the different CTO options and how do they work?
Answer:
The different options in CTO to reduce skew are described in the following list：
1、Buffer and Gate Sizing
Sizes up or down buffers and gates to improve both skew and insertion delay.
You can impose a limit on the type of buffers and gates to be used. No new clock tree hierarchy will be introduced during this operation. See figure 1.
2、Buffer and Gate Relocation
Physical location of the buffer or gate is moved to reduce skew and insertion delay. No new clock tree hierarchy will be introduced during this operation. See figure 2.
3、Level Adjustment
Adjust the level of the clock pins to a higher or lower part of the clock tree hierarchy. No new clock tree hierarchy will be introduced during this operation. See figure 3.
4、Reconfiguration
Clustering of sequential logic. Buffer placement is performed after clustering.
Longer runtimes. No new clock tree hierarchy will be introduced during this operation. See figure 4.
5、Delay Insertion
Delay is inserted for shortest paths. Delay cells can be user defined or can be extracted from by the tool. By adding new buffers to the clock path the clock tree hierarchy will change. See figure 5.
6、Dummy Load Insertion
