么在ALLEGRO里统计焊盘和包括芯片pin和阻容的pad? 板子要拿出去布,需要根据焊盘计费?
Drawing Statistics:
Drawing Extents XL(-250.0000) YL(-250.0000) XU(350.0001) YU(350.0001) Dimensions in millimeters with 4 decimal places
Package Symbols: Total(845) Mirrored(123) Pins(4539)
Mechanical Symbols: Total(0) Mirrored(0) Pins(0)
Format Symbols: Total(0)
DRC: Errors(95) UP TO DATE
Padstack Definitions: 108
Functions: Assigned(847) Unassigned(0) Total(847)
Layout Statistics:
Components: Placed(845) Unplaced(0) Total(845)
Nets: W/Rats(1110) No/Rats(0) Total(1110)
Pins: W/Rats(4277) No/Rats(0) Unused(262) Unplaced(0) Total(4539)
Equivalent ICs (1 pin = 1/14 EIC): 324
RatTs: 0
Router Keepin (in): (-6.2615,-3.9367) by (6.2969,4.2910)
Layout area (sq in): 103.32
Layout density (sq in/EIC): 0.319
Pin density (Pins/sq in): 43.930
Double-sided layout area (sq in): 206.65
Double-sided layout density (sq in/EIC): 0.159
Double-sided pin density (Pins/sq in): 21.965
Average ratlength (in): 1.6
Rat density (in/sq in): 35.103
Double-sided rat density (in/sq in): 17.552
Connection Statistics:
Connections: W/Rats(3167) No/Rats(0) Total(3167)
Already Connected: W/Rats(3167) No/Rats(0) Total(3167)
Missing Connections: W/Rats(0) No/Rats(0) Total(0)
Dangling Connections (See logfile): 8
Connection Completion: W/Rats(100.00%) No/Rats(0.00%) Total(100.00%)
Manh Distance (inches): 3627.0349
Etch Length (inches): W/Rats(3765.48) No/Rats(0.00) Total(3765.48)
Number of Vias: W/Rats(2685) No/Rats(0) Total(2685)
Vias per Connection: W/Rats(0.85) No/Rats(0.00)Total(0.85)
SMD pins with attached clines: 3435
Etch Statistics:
Layer | Clines/Carcs | Shapes(voids) | Rectangles | Lines/Arcs | Text |
TOP | 3128 | 87(21) | 0 | 0 | 0 |
SGND | 0 | 2(0) | 0 | 0 | 0 |
IN1 | 410 | 15(211) | 0 | 0 | 0 |
SVCC | 0 | 8(0) | 0 | 0 | 0 |
IN2 | 131 | 11(271) | 0 | 0 | 0 |
IN3 | 268 | 9(113) | 0 | 0 | 0 |
SGND1 | 0 | 2(0) | 0 | 0 | 0 |
BOTTOM | 299 | 27(211) | 0 | 0 | 0 |
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