/arch:IA32
(i32 only)
Generates code that will run on any Pentium or later processor.
OFF
/arch:SSE3 (i32, i64em)
Optimizes for Intel® Streaming SIMD Extensions 3 (Intel® SSE3).
OFF
/arch:SSSE3 (i32, i64em)
Optimizes for Intel® Supplemental Streaming SIMD Extensions 3 (Intel® SSSE3).
OFF
/arch:SSE4.1 (i32, i64em)
Optimizes for Intel® Streaming SIMD Extensions 4 Vectorizing Compiler and Media Accelerators.
OFF
/GS
(i32, i64em)
Determines whether the compiler generates code that detects some buffer overruns.
/GS-
/QaxSSE2
(i32, i64em)
Can generate Intel® SSE2 and SSE instructions for Intel processors, and it can optimize for Intel® Pentium® 4 processors, Intel® Pentium® M processors, and Intel® Xeon® processors with Intel® SSE2.
OFF
/QaxSSE3
(i32, i64em)
Can generate Intel® SSE3, SSE2, and SSE instructions for Intel processors and it can optimize for processors based on Intel® Core™ microarchitecture and Intel NetBurst® microarchitecture.
OFF
/QaxSSSE3
(i32, i64em)
Can generate Intel® SSSE3, SSE3, SSE2, and SSE instructions for Intel processors and it can optimize for the Intel® Core™2 Duo processor family.
OFF
/QaxSSE4.1
(i32, i64em)
Can generate Intel® SSE4 Vectorizing Compiler and Media Accelerator instructions for Intel processors. Can generate Intel® SSSE3, SSE3, SSE2, and SSE instructions and it can optimize for Intel® 45nm Hi-k next generation Intel® Core™ microarchitecture.
OFF
/QaxSSE4.2
(i32, i64em)
Can generate Intel® SSE4 Efficient Accelerated String and Text Processing instructions supported by Intel® Core™ i7 processors. Can generate Intel® SSE4 Vectorizing Compiler and Media Accelerator, Intel® SSSE3, SSE3, SSE2, and SSE instructions and it can optimize for the Intel® Core™ processor family.
OFF
/Qdiag-error-limit:n
Specifies the maximum number of errors allowed before compilation stops.
n=30
/Qdiag-once:id[,id,...]
Tells the compiler to issue one or more diagnostic messages only once.
OFF
/Qfast-transcendentals
Enables the compiler to replace calls to transcendental functions with faster but less precise implementations.
OFF
/Qfma
(i64 only)
Enables the combining of floating-point multiplies and add/subtract operations.
ON
/Qfp-relaxed
(i64 only)
Enables use of faster but slightly less accurate code sequences for math functions.
OFF
/Qinstruction:[no]movbe
(i32, i64em)
Determines whether MOVBE instructions are generated for Intel processors.
ON
/Qopenmp-link:library
Controls whether the compiler links to static or dynamic OpenMP run-time libraries.
/Qopenmp-link:dynamic
/Qopenmp-threadprivate:type
Lets you specify an OpenMP* threadprivate implementation.
/Qopenmp-threadprivate:legacy
/Qopt-block-factor:n
Lets you specify a loop blocking factor.
OFF
/Qopt-jump-tables:keyword
Enables or disables generation of jump tables for switch statements.
/Qopt-jump-tables:default
/Qopt-loadpair
(i64 only)
Enables loadpair optimization.
/Qopt-loadpair-
/Qopt-mod-versioning
(i64 only)
Enables versioning of modulo operations for certain types of operands.
/Qopt-mod-versioning-
/Qopt-prefetch-initial-values
(i64 only)
Enables or disables prefetches that are issued before a loop is entered.
/Qopt-prefetch-initial-values
/Qopt-prefetch-issue-excl-hint
(i64 only)
Determines whether the compiler issues prefetches for stores with exclusive hint.
/Qopt-prefetch-issue-excl-hint-
/Qopt-prefetch-next-iteration
(i64 only)
Enables or disables prefetches for a memory access in the next iteration of a loop.
/Qopt-prefetch-next-iteration
/Qopt-subscript-in-range
(i32, i64em)
Determines whether the compiler assumes no overflows in the intermediate computation of subscript expressions in loops.
/Qopt-subscript-in-range-
/Qprof-data-order
Enables or disables data ordering if profiling information is enabled.
/Qprof-data-order
/Qprof-func-order
Enables or disables function ordering if profiling information is enabled.
/Qprof-func-order
/Qprof-hotness-threshold
Lets you set the hotness threshold for function grouping and function ordering.
OFF
/Qprof-src-dir
Determines whether directory information of the source file under compilation is considered when looking up profile data records.
/Qprof-src-dir
/Qprof-src-root
Lets you use relative directory paths when looking up profile data and specifies a directory as the base.
OFF
/Qprof-src-root-cwd
Lets you use relative directory paths when looking up profile data and specifies the current working directory as the base.
OFF
/Qtcollect-filter
Lets you enable or disable the instrumentation of specified functions.
OFF
/Quse-msasm-symbols
(i32, i64em)
Tells the compiler to use a dollar sign ("$") when producing symbol names.
OFF
/Qvc9
(i32, i64em)
Specifies compatibility with Microsoft* Visual Studio 2008.
varies
/Qvec
(i32, i64em)
Enables or disables vectorization and transformations enabled for vectorization.
/Qvec
/QxHost
(i32, i64em)
Can generate specialized code paths for the highest instruction set and processor available on the compilation host.
OFF
/QxSSE2
(i32, i64em)
Can generate Intel® SSE2 and SSE instructions for Intel processors, and it can optimize for Intel® Pentium® 4 processors, Intel® Pentium® M processors, and Intel® Xeon® processors with Intel® SSE2.
ON
/QxSSE3
(i32, i64em)
Can generate Intel® SSE3, SSE2, and SSE instructions for Intel processors, and it can optimize for processors based on Intel® Core™ microarchitecture and Intel NetBurst® microarchitecture.
OFF
/QxSSE3_ATOM
(i32, i64em)
Can generate MOVBE instructions for Intel processors and it can optimize for the Intel® Atom™ processor and Intel® Centrino® Atom™ Processor Technology.
OFF
/QxSSSE3
(i32, i64em)
Can generate Intel® SSSE3, SSE3, SSE2, and SSE instructions for Intel processors and it can optimize for the Intel® Core™2 Duo processor family.
OFF
/QxSSE4.1
(i32, i64em)
Can generate Intel® SSE4 Vectorizing Compiler and Media Accelerator instructions for Intel processors. Can generate Intel® SSSE3, SSE3, SSE2, and SSE instructions and it can optimize for Intel® 45nm Hi-k next generation Intel® Core™ microarchitecture.
OFF
/QxSSE4.2
(i32, i64em)
Can generate Intel® SSE4 Efficient Accelerated String and Text Processing instructions supported by Intel® Core™ i7 processors. Can generate Intel® SSE4 Vectorizing Compiler and Media Accelerator, Intel® SSSE3, SSE3, SSE2, and SSE instructions and it can optimize for the Intel® Core™ processor family.
OFF
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