Posted: Fri May 29, 2009 2:30 am Post subject: different timescale confusion
Hi,
I am working on one module and I have specified below time scale in my first life of testbench file.
`timescale 1ns/10fs
But when I am doing compilation through vcs , I am getting following display for time scale.
TimeScale is 1 ps / 10 fs
As I am working on single module, there might be different time scales set from different files.
I would like to know that which will be the final time scale will be used in simulation ? Is it the one which is shown by VCS (i.e. 1 ps / 10 fs) ?
If this is the case, then I have to change delays in my env wherever I have used # .
About precision, I thiink the smallest one will be selected but still not sure about it.
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>>About precision, I thiink the smallest one will be selected but still not sure about it.
Yes smallest precision and unit will take for total simulation but the it will not use in the modules.
“-timescale” normally usefull to mention timescale for the modules which left without mention.
You can use -override_timescale=<time_unit>/<time_precision> for unique timescale for all modules.
If you are not willing to change. Then check timescale with $printimescale() system task and mention # s according to that.
You can find some more info @
http://www.systemverilog.in/forum/showthread.php?tid=9
